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1 of 28 040202 features single element 256-position linear taper potentiometer supports potentiometer terminal working voltages up to 11v potentiometer terminal voltage independent of supply voltage potentiometer wiper position controlled and read over minimal 1-wire bus interface 100 k resistor element value t0-92 package provides a 1-wire ? variable resistor configuration supports conditional search based on power-on default wiper position multiple DS2890?s can be identified on a common 1-wire bus and operated independently unique factory lasered 64-bit registration number assures error free device selection and absolute part identity built-in multi-drop controller ensures compatibility with other 1-wire network products supports overdrive mode which boosts communication speed up to 142 kbits per second -40 o c to +85 o c operating temperature range 2.8v ? 6.0v operating voltage range pin assignment top view 6-pin tsoc 1-wire gnd vdd 1 2 3 6 5 4 rh wiper rl to-92 package 123 gnd 1-wire rh 123 bottom view flip chip package side view top view visit www.dalsemi.com for flip chip pinout and mechanical data. ordering information part number resistance * package description DS2890-000 100 k t0-92 DS2890p-000 100 k 6-pin tsoc DS2890x-000 100 k flip chip pkg., tape & reel DS2890-000/t&r 100 k tape & reel of DS2890 DS2890p-000/t&r 100 k tape & reel of DS2890p * contact the factory for availability of alternate resistance values www.maxim-ic.com DS2890 1-wire di g ital potentiomete r 1-wire is a registered trademark of dallas semiconductor.
DS2890 2 of 28 pin description signal name type function 1-wire i/o 1-wire bus interface. open drain, requires external pull-up resistor. range: 2.8v ? 6.0v. see hardware confi guration for pull-up resistor recommendations. rh i/o high end terminal of potentiometer resistor element. range: 0v ? 11.0v. range independent of 1-wire or v dd supply levels as well as the voltage levels applied to the other potentiometer terminals. rl i/o low end terminal of potentiometer re sistor element. range: 0v ? 11.0v. range independent of 1-wire or v dd supply levels as well as the voltage levels applied to the other potentiometer terminals. wiper i/o potentiometer wiper terminal. ra nge 0v ? 11.0v. range independent of 1-wire or v dd supply levels as well as the voltage levels applied to the other potentiometer terminals. v dd pwr auxiliary power supply input. range: 2.8v ? 6.0v gnd pwr ground description the DS2890 is a linear taper digitally controlle d potentiometer with 256 wiper positions. device operation, including wiper position, is controlled over the single contact 1-wire bus for the ultimate in electrical interface simplicity. with a wide 0?11 volt working voltage range for the potentiometer terminals, the DS2890 is ideal for a broad range of industrial and control app lications. potentiometer terminal voltage is inde pendent of device supply voltage as well as the voltage applied to the other potentiometer terminals. comm unication with the DS2890 follows the standard dallas semiconductor 1-wire protocol and can be accomplished with min imal hardware such as a single port pin of a microcontroller. multiple DS2890 devices can re side on a common 1-wire bus and be operated independently of each other. each DS2890 has its own unalterable 64-bit ro m registration number that is factory lasered into the chip. the registration number guarantees unique identification for absolute traceability and is used to address the device in a multi-drop 1-wire network environment. the DS2890 will respond to a 1-wire conditional search command if the potentiomete r wiper is set at the power-on default position. this feature enables the bus mast er to easily determine whether a potentiometer has gone through a power-on reset and needs to be re-configured with a required wiper position setting. the DS2890 supports two power modes: a) 1-wire only mode in which device power is supplied parasitically from the 1-wire and b) v dd mode where power is supplied from an external supply with a v dd supply the device can support both a potentiometer and variable resistor configuration. when operating in a 1- wire only power mode the device supports only a variable resistor configuration.
DS2890 3 of 28 operation the DS2890 is a single element digital potentiometer; a block diagram of the device is shown in figure 1. the device has a total of 256 linearly spaced tap points including the rl and rh terminals; a total of 255 resistive segments exist between the rl and rh terminals. these tap points are accessible to the wiper terminal whose position is controlled via the 1-wire bus interface. wiper position and device state are maintained as long as the 1-wire bus is active or the v dd supply is applied within operating limits. otherwise, a power-on reset will occur and the wiper position and operating state will return to power-on default conditions. figure 1. DS2890 block diagram as shown in the figure the device has five major elements: the 1-wire function controller, the potentiometer controller, the 64-bit rom, the resistor ar ray, and parasite power circuitry. each of these elements is discussed in detail throughout the rema inder of the data sheet. DS2890 control including device selection, positioning/reading the potentiometer wiper, and device operating state is performed over the 1-wire bus. the hierarchical structure of the 1-wire protocol as applicable to the DS2890 is shown in figure 2. as shown, the control sequence starts with the 1-wire bus master issuing one of eight rom function commands. after a rom function command is successfully completed potentiometer functions may be executed. the protocol for rom and potentiometer functions are described in the ?command flow? section . for the 3-pin to-92 package c onfiguration and operation see the ?to-92 package operation? section.
DS2890 4 of 28 figure 2. 1-wire command hierarchical structure data i/o bit order all data is read and written least significant bit (lsb) first. potentiometer feature register although the feature set of the DS2890 is primarily fi xed, a mechanism to identify feature characteristics of future 1-wire potentiometers has been developed and impleme nted in the DS2890. as shown in figure 3, the feature register is an encoded read-onl y byte that describes the characteristics of the DS2890 and future 1-wire potentiometers. feature values that correspond to the DS2890 are highlighted. the feature register is read with the read control register potentiometer function command (see ?potentiometer function commands?).
DS2890 5 of 28 figure 3. 1-wire potentiometer feature register feature register bit encoding b7 b6 b5 b4 b3 b2 b1 b0 pr nwp np wsv pc feature register bit definitions feature description bit(s) definition if 0: logarithmic potentiometer element(s) pc: potentiometer characteristic b0 if 1: linear potentiometer element(s) if 0: wiper setting(s) are non-volatile wsv: wiper setting volatility b1 if 1: wiper setting(s) are volatile np: number of potentiometers b3..b2 2 bit binary value representing number of potentiometers: if 00b: 1 potentiometer if 01b: 2 potentiometers if 10b: 3 potentiometers if 11b: 4 potentiometers nwp: number of wiper positions b5..b4 2 bit binary value representing number of wiper positions for each potentiometer: if 00b: 32 positions if 01b: 64 positions if 10b: 128 positions if 11b: 256 positions pr: potentiometer resistance b7..b6 2 bit binary value representing potentiometer resistance: if 00b: 5 k if 01b: 10 k if 10b: 50 k if 11b: 100 k DS2890 feature values are highlighted: value the DS2890 will respond with a feature regis ter value of f3h when a read control register command is executed, see se ction ?potentiometer function commands?. potentiometer control register the potentiometer control register is used to turn on/off the DS2890 charge pump (see section ?potentiometer wiper resistance and c harge pump consid erations? for a discussion of the charge pump) and has control capabilities for future 1-wire potentiometers that could contain multiple resistor elements. the format of the control register is shown in figure 4.
DS2890 6 of 28 figure 4. potentiometer control register control register bit encoding b7 b6 b5 b4 b3 b2 b1 b0 xcpc x x wn wn control register bit definitions* description bit(s) definition wn: wiper number to control b1..b0 2 bit binary value representing the potentiometer wiper to control: if 00b: potentiometer 1 wiper if 01b: potentiometer 2 wiper if 10b: potentiometer 3 wiper if 11b: potentiometer 4 wiper wn : inverted wiper number to control b3..b2 1?s complement of potentio meter wiper to control: if 11b: potentiometer 1 wiper if 10b: potentiometer 2 wiper if 01b: potentiometer 3 wiper if 00b: potentiometer 4 wiper if 0: the charge pump is off cpc: charge pump control b6 if 1: the charge pump is on x: don?t care. b4,b5,b7 these bits are reserved for future use by dallas semiconductor. these bits should be written to a value of 0. *note: control register power-on defaults: charge pump is off (cpc=0), wiper number to control is wiper #1 (wn=00b, wn =11b). valid DS2890 control values are highlighted: value thus for the DS2890, valid control register values are: control register value description 00001100b charge pump off, potentiometer #1 wiper selected 01001100b charge pump on, potentiometer #1 wiper selected as shown in figure 22 and discussed in the ?potentiometer function commands? section, no change in device state will occur if an invalid control register value is sent.
DS2890 7 of 28 power and configuration considerations 1-wire devices can typically derive operating power entirely from the 1-wire bus by storing energy on an internal capacitor during periods of time when the 1-wire bus is in a high state. during bus low times the device continues to operate from the energy stored on the internal capacitor; the capacitor is then recharged when the bus returns to a high state. this technique of operating entirely from the 1-wire bus by powering from energy stored on an internal capacitor during bus low times in known as ?parasite powered? operation. special consideration is required with the DS2890 in that it supports two power configurations and two rela ted digital resistor modes: potentiome ter configuration a nd variable resistor configuration. the potentiometer configuration requires the presence of a vdd power source to supply the power needs of the device charge pump which mu st be turned on to support a terminal-to-terminal wiper output range. the variable resistor configuration is supported with or without a vdd source or enabled charge pump although resistan ce range, as described below, is influenced by the charge pump state. potentiometer configuration to configure and operate the DS2890 as a potentiometer as shown in figure 5 requires the tsoc or flip chip package, a vdd power source, and the devi ce charge pump turned on (control register, bit cpc=1). the charge pump must be enabled to support rl to rh terminal voltage swings at the wiper output and as described previously, a vdd supply must be provided to support the power requirements of the charge pump. figure 5. potentiometer configuration rh wiper rl vdd 1-wire gnd 2.8v to 6.0v 2.8v to 6.0v bus master variable resistor configuration the variable resistor configura tion as shown in figure 6 is supported by all package types with or without an external vdd supply. as described pr eviously, without a vdd source the charge pump must be disabled.
DS2890 8 of 28 figure 6. variable resistor configurations (to92 package) rh wiper rl vdd 1-wire gnd 2.8v to 6.0v or no connect 2.8v to 6.0v bus master rh 1-wire gnd 2.8v to 6.0v bus master wiper resistanceconsiderations a simplified diagram of the DS2890 resistor array for the potentiometer configuration is shown in figure 8 . in this figure the r ds resistance of the wiper transistors in figure 1 are modeled as wiper resistance r wiper . the value of r wiper varies with device configurati on, operational state, and wiper terminal voltage. wiper resistance is significantly reduced when an external vdd supply is used and the device charge pump is enabled. a wiper resistance graph with the charge pump enabled is shown in figure 10 . figure 8. potentiometer resistor model rh r wiper rl wiper
DS2890 9 of 28 figure 10. typical wiper resistan ce vs wiper voltage at 25 o c, charge pump on 100 1000 0.1 5.5 11 voltage across wiper (v) wiper resistance (ohms) when packaged in a 3-pin to-92 or configured as a variable resistor, the DS2890 takes on a configuration as shown in figure 11 , a simplified model is shown in figure 12. as shown, the rl and wiper terminals and are connected to gnd and the resistance between the rh terminal and gnd is varied. as described previously, the DS2890 charge pum p must be turned off (default state) for operation with the to-92 package or when vdd is not applied. wiper resistance for a configuration with the charge pump disabled is shown in figure 13 .
DS2890 10 of 28 figure 11. DS2890 to-92 configuration block diagram figure 12. variable resistor model rh r wiper
DS2890 11 of 28 figure 13. typical wiper resistan ce vs wiper voltage at 25 o c, charge pump off 0.1 1 10 100 0246810 voltage across wiper (volts) wiper resistance (kohms) v pu =2.8v v pu =5v v pu =6v 64-bit lastered rom each DS2890 contains a unique and una lterable lasered rom registration num ber that is 64 bits long; the format of this value is shown in figure 15. the firs t 8 bits are a 1-wire family code; the family code for the DS2890 and future 1-wire potentio meters is 2ch. the next 48 bits are a unique serial number that is administered by dallas semiconductor. the last 8 bits are a crc of the first 56 bits. the 1-wire crc is generated using a polynomial generator consisting of a shift register and xor gates as shown in figure 16. operationally, the crc generator works as follows: th e shift register bits are first initialized to zero. then starting with the least significant bit, the 8-bit family code is shifted in. after the 8th bit of the family code has been entered, the 48-bit serial number is shifted in. after shifting in the 48th bit of the serial number the shift register contains the crc valu e. shifting in the 8 bits of crc should return the shift register to an all zeros value. the 64-bit ro m and the 1-wire function controller portions of the DS2890 allow the device to operate as a 1-wire devi ce and follow the protocol detailed in the section ?transaction sequence?. figure 15. 64-bit lasered rom msb lsb 8-bit crc code 48-bit serial number 8-bit family code (2ch) msb lsb msb lsb msb lsb
DS2890 12 of 28 figure 16. 1-wire crc generator r x 2 x 1 x 0 x 8 x 7 x 6 x 5 x 4 x 3 8th stage 7th stage 6th stage 5th stage 4th stage 3rd stage 2nd stage 1st stage s input data polynomial = x 8 + x 5 + x 4 + 1 potentiometer function commands once the bus master has completed a rom co mmand sequence, one of six DS2890 potentiometer function commands can be issued. the potentio meter function command flow charts, figure 21 and figure 22, describe the protocols necessary for ad justing or reading the potentiometer wiper position or controlling the operating state of the DS2890. all potentiometer functions consist of a single command byte followed by one or more bytes of data or control written/read by the bus master. all data transferred between the DS2890 and the bus master are communicated least significant bit first. read position [f0h] the read position command is used to obtain the wiper setting of the potentiometer currently addressed by the control register. although the DS2890 is a single element potentiometer, wiper addressing still applies and the control register wiper number used for addressing must be set accordingly. in addition to wiper position, the control register byte will be returned with a read position command. this enables the bus master to easily confirm/determine the currently addressed potentiometer wiper. following the read position command byte, the bus master reads 16 bits to obtain first the control register byte then the wiper position byte. the DS2890 will respond with 0?s to additional reads after the 8 bit of the position byte. the read position command is terminated with a reset pulse. write position [0fh] the write position command is used to set the positi on of the currently addressed potentiometer wiper. although the DS2890 is a single element potentiometer, wiper addressing still applies and the control register wiper number used for addressing must be set accordingly. the bus master follows the write position command byte with an 8-bit wiper position value. following the 8th bit of the position byte, the bus master reads back the 8-bit position value from the DS2890 to confirm that the value was received correctly by the device. if an incorrect value is read back, the bus master must issue a reset pulse and repeat the sequence. if the value read back is co rrect, the bus master then sends the 8-bit release code (96h). if the DS2890 accurately receives the releas e code, the wiper position is updated and the device will respond with 0?s to additional reads by the bus ma ster. if an invalid release code is received, no change is made to the wiper position and the device will respond with 1?s to additional reads by the bus master. the write position command is terminated with a reset pulse.
DS2890 13 of 28 read control register [aah] the read control register command is used to obtain both the control register and potentiometer feature register. following the read control register command byte, the bus master reads 16 bits to obtain first the feature register byte and then th e control register byte. the DS2890 will respond with 0?s to additional reads after the 8 bit of the control register byte. the read control register command is terminated with a reset pulse. write control register [55h] the write control register command is used to ma nipulate DS2890 state bits located in the control register. this command is used to set the potentio meter wiper address and charge pump state. the bus master follows the write control register command byte with an 8-bit register value. following the 8th bit of the register byte, the bus master reads back the 8-bit control value from the DS2890 to confirm that the device received the correct valu e (note that if an invalid regist er value was received by the DS2890, the bus master will read all 1?s (ffh) during the read back sequence.). if a value other than ffh is read, the bus master determines if the ds 2890 received the correct value. if an incorrect value is read back, the bus master must issue a reset pulse and repeat the sequence. if the value read back is correct, the bus master then sends the 8-bit release code (96h). if the DS2890 accurately receives the release code, the control register is updated and the device will respond with 0?s to additional reads by the bus master. if an invalid release code is received, no change is made to the control register and the device will respond with 1?s to additional reads by the bus master. the write control register command is terminated with a reset pulse. increment [c3h] the increment command is used for a one step position increase of the currently addressed potentiometer wiper. although the DS2890 is a single element potentiometer, wiper addressing still applies and the control register wiper number used for addressing must be set accordingly. the bus master follows the increment command byte with an 8-bit read to wh ich the DS2890 will respond with the new 8-bit wiper position set point. no position change is made if the DS2890 wiper is at the maximum position (ffh) and an increment command is received. one difference between the increment/decrement commands and other potentiometer functions is that upon completion of either of these commands, 1-wire command processing remains at the potentiometer function level. as shown in figure 21, additional potentiometer commands may be sent without goin g through the rom function flow. decrement [99h] the decrement command is used for a one step position decrease of the currently addressed potentiometer wiper. although the DS2890 is a singl e element potentiometer, wiper addressing still applies and the control register wiper number used for addressing must be set accordingly. the bus master follows the decrement command byte with an 8-bit read to which the DS2890 will respond with the new 8-bit wiper position set point. no position change is made if the DS2890 wiper is at the minimum position (00h) and a decrement command is received. one difference between the increment/decrement commands and other potentiometer functions is that upon completion of either of these commands, 1-wire command processing remains at the potentiometer function level. as shown in figure 21, additional potentiomete r commands may be sent without going through the rom function flow.
DS2890 14 of 28 1-wire bus system the 1-wire bus is a system, which has a single bus master and one or more slaves. in all instances the DS2890 is a slave device. the bus mast er is typically a microcontroller. the discussion of this bus system is broken down into three topics: ha rdware configuration, transacti on sequence, and 1-wire signaling (signal types and timing). the 1-wire protocol defines bus transactions in terms of the bus state during specific time slots that are initiated on the falling edge of sync pulses from the bus master. hardware configuration the 1-wire bus has only a single line by definition; it is important that each device on the bus be able to drive it at the appropriate time. to facilitate this, each device attached to the 1-wire bus must have open drain or 3-state outputs. the 1-wire port of the DS2890 is open drain with an internal circuit equivalent to that shown in figure 9. a multi-drop bus consists of a 1-wire bus with multiple slaves attached. at regular speed the 1-wire bus has a maximum data rate of 16.3 kbits per second. the speed can be boosted to 142 kbits per second by activating the overdriv e mode. for a discrete bus master interface as in figure 17, the 1-wire bus requires a pull-up resistor with a minimum value of 2.2 k . depending on 1-wire communication speed, regular or overdrive, and bus load characteristics, the optimal pull-up resistor value will be in the 1.5 k to 5 k range. figure 18 shows a ds 2480b bus master configuration with an interface to the host cpu serial port. am ong many features, the ds2480b simplifies the 1-wire interface design, generates slew-rate controlled 1-wire waveforms, and off-loads 1-wire timing generation overhead required in a discrete solution. the idle state for the 1-wire bus is high. if for an y reason a transaction needs to be suspended, the bus must be left in the idle state if the transaction is to resume. if this does not occur and the bus is left low for more than 16 s (overdrive speed) or more than 120 s (regular speed), one or more devices on the bus may be reset. figure 17. hardware configuration rx tx open drain port pin 5 a typ. DS2890 1-wire port rx = receive tx = transmit bus master v pup data rx tx mosfet 100 see text note: depending on 1-wire communication speed, regular or overdrive, and bus load characteristics, the optimal pull-up resistor value will be in the 1.5 k to 5 k range.
DS2890 15 of 28 figure 18. bus master with ds2480b driver vdd pol rxd txd vpp 1-w gnd nc ds2480b +5v to 1-wire connection of DS2890 serial in serial out host cpu serial port bus master transaction sequence the protocol for accessing the DS2890 vi a the 1-wire port is as follows: initialization rom function command potentiometer function command transaction/data initialization all transactions on the 1-wire bus begin with an initialization sequence. the initialization sequence consists of a reset pulse transmitted by the bus master followed by presence pulse(s) transmitted by the slave(s). the presence pulse lets the bus master know that the DS2890 is on the bus and is ready to operate. for more details, see the ?1-wire signaling? section. rom function commands once the bus master has detected a presence, it can issue one of the eight rom function commands that the DS2890 supports. all rom function commands are 8 bits long. a list of these commands follows (refer to figure 23 and figure 24 flowcharts): read rom [33h] this command allows the bus master to read th e DS2890?s 8-bit family code, unique 48-bit serial number, and 8-bit crc. this command should only be used if there is a single slave on the bus. if more than one slave is present on the bus, a data collision will occur when all slaves try to transmit at the same time (open drain will produce a wired-and result). the resultant family code and 48-bit serial number read by the master will be invalid. match rom [55h] the match rom command, followed by a 64-bit rom se quence, allows the bus master to address a specific DS2890 on a multi-drop bus. only the DS2890 that exactly matches the 64-bit rom sequence will respond to the following memory function comma nd. all slaves that do not match the 64-bit rom sequence will wait for a reset pulse. this command can be used with a single or multiple devices on the bus.
DS2890 16 of 28 search rom [f0h] when a multi-drop system is initially brought up, the bus master might not know the number of devices on the 1-wire bus or their 64-bit rom codes. the se arch rom command allows the bus master to use a process of elimination to identify the 64-bit rom code s of all slave devices on the bus. the search rom process is the repetition of a simple 3-step routine: r ead a bit, read the complement of the bit, then write the desired value of that bit. the bus master performs this 3-step routine on each bit of the rom. after one complete pass, the bus master knows the 64-b it rom code of one device. additional passes will identify the rom codes of the remaining devices. conditional search rom [ech] the conditional search rom command operates similarly to the search rom command except that only devices fulfilling the specified search condition will pa rticipate in the search. the device condition that will cause individual DS2890s to participate in a conditional search is a wiper position located at the power-on default setting (00h). this feature enables the bus master to easily determine whether a potentiometer has gone through a pow er-on reset and needs to be re-c onfigured with a required wiper position setting. skip rom [cch] this command can save time in a single drop bus system by allowing the bus master to access potentiometer functions without providi ng the 64-bit rom code. if more than one slave is present on the bus and, for example, a read command is issued following the skip rom command, data collision will occur on the bus as multiple slaves transmit simulta neously (open drain pull-downs will produce a wired- and result). overdrive skip rom [3ch] on a single-drop bus this command can save time by allowing the bus master to access the memory functions without providing the 64-bit rom c ode. unlike the normal skip rom command the overdrive skip rom sets the DS2890 in the ov erdrive mode. all communication following this command code has to occur at overdrive speed until a reset pulse of minimum 480 s duration resets all devices on the bus to regular speed. when issued on a multi-drop bus this command will se t all overdrive-supporting devices into overdrive mode. to subsequently address a sp ecific overdrive-supporting device, a reset pulse at overdrive speed has to be issued followed by a match rom or search rom command sequence. this will speed up the search process. if more than one overdrive-supportin g slave is present on the bus and the overdrive skip rom command is followed by a read command, data collision will occur on the bus as multiple slaves transmit simultaneously (open drain pu ll-downs will produce a wire-and result). overdrive match rom [69h] the overdrive match rom command, followed by a 64-bit rom sequence transmitted at overdrive speed, allows the bus master to address a specific DS2890 on a multi-drop bus and to simultaneously set it in overdrive mode. only the DS2890 that exactly matches the 64-bit rom sequence will respond to the subsequent potentiometer function command. slav es already in overdrive mode from a previous overdrive skip or a successful overdrive match command will remain in overdrive mode. all over- drive-capable slaves will return to regular speed at the next reset pulse of minimum 480 s duration. the overdrive match rom command can be used with a single or multiple devices on the bus.
DS2890 17 of 28 resume command [a5h] in a typical application the DS2890 may be accessed seve ral times to complete a control adjustment. in a multi-drop environment this means that the 64-bit rom sequence of a match rom command has to be repeated for every access. to maximize the data throughput in a multi-drop environment the resume command function was implemented. as shown in figure 24, this function checks the status of the rc flag and, if it is set, directly transfers control to the potentiometer functions, similar to a skip rom command. the only way to set the rc flag is thr ough successfully executing the match rom, search rom, conditional search rom, or overdrive ma tch rom command. once the rc flag is set, the device can repeatedly be accessed through the resu me command function. acce ssing another device on the bus will clear the rc flag, preventing two or more devices from simultaneously responding to the resume command function. potentiometer function example at regular speed with an auxiliary supply (v dd within range): turn on the charge pump, set the wiper position to mid-point, increment the wiper twice, and decrement the wiper once. master mode data (lsb first) comments tx reset reset pulse (480 - 960 s) rx presence presence pulse tx cch issue skip rom command tx 55h issue write control register command tx 4ch issue control register value for wn=0, cpc=1 rx read back control register value (4ch) and verify tx 96h issue release code to update control register rx if 0?s are read, update was successful; if 1?s are read, the update failed tx reset reset pulse (480 - 960 s) rx presence presence pulse tx cch issue skip rom command tx 0fh issue write position command tx 7fh write wiper position value rx read back wiper position byte and verify tx 96h issue release code to update wiper position rx if 0?s are read, update was successful; if 1?s are read, the update failed tx reset reset pulse rx presence presence pulse tx cch issue skip rom command
DS2890 18 of 28 master mode data (lsb first) comments tx c3h issue wiper increment command rx read new wiper position tx c3h issue wiper increment command rx read new wiper position tx 99h issue wiper decrement command rx read new wiper position tx reset reset pulse 1-wire signaling the DS2890 requires strict protocols to ensure data integrity. the prot ocol consists of four types of signaling on one line: reset sequence with reset pulse and presence pulse, write 0, write 1 and read data. except for the presence pulse the bus master initiates all these signals. the DS2890 can communicate at two different speeds, regular speed and overdrive speed. if not explicitly set into the overdrive mode, the DS2890 will communicate at regular speed. while in overdrive mode the fast timing applies to all waveforms. the initialization sequence required to begin any communication with the DS2890 is shown in figure 19. a reset pulse followed by a presence pu lse indicates the DS2890 is ready to send or receive data. the bus master transmits (tx) a reset pulse (t rstl , minimum 480 s at regular speed, 48 s at overdrive speed). the bus master then releases the line and goes into receive mode (rx). the 1-wire bus is pulled to a high state via the pull-up resistor. aft er detecting the rising edge on the data contact, the DS2890 waits (t pdh , 15-60 s at regular speed, 2-6 s at overdrive speed) and then transmits the presence pulse (t pdl , 60-240 s at regular speed, 8-24 s at overdrive speed). a reset pulse of 480 s or longer will exit the overdrive mode returning the device to regular speed. if the DS2890 is in overdrive mode and the reset pulse is no longer than 80 s the device will remain in overdrive mode. read/write time slots the definitions of write and read time slots are illustrated in figure 20 (a-c). the master initiates all time slots by driving the data line low. the falling edge of the data line synchronizes the DS2890 to the master by triggering an internal timing circuit. during wr ite time slots, the timing circuit determines when the DS2890 will sample the data line. for a read data time slot, if a ?0? is to be transmitted, the timing circuit determines how long the DS2890 will hold the data line low. if the data bit is a ?1?, the DS2890 will not hold the data line low at all.
DS2890 19 of 28 figure 19. initialization procedure ?reset and presence pulses? resistor master DS2890 master rx "presence pulse" regular speed overdrive speed 480 s t rstl < * 480 s t rsth < ** 15 s t pdh < 60 s 60 t pdl < 240 s 48 s t rstl < 80 s 48 s t rsth < ** 2 s t pdh < 6 s 8 t pdl < 24 s master tx "reset pulse" v pullup v pullup min v ih min v il max 0v t rsth t rstl t pdh t pdl t r * in order not to mask interrupt signaling by ot her devices on the 1-wire bus and to prevent a power- on reset of the parasite powered circuit, t rstl + t r should always be less than 960 s. ** includes recovery time. figure 20. read/write timing diagrams a) write-one time slot 15s (od: 2s) 60s (od: 6s) DS2890 sampling window v pullup v pullup min v ih min v il max 0v t slot t rec t low1 regular speed overdrive speed 60 s t slot < 120 s 1 s t low1 < 15 s 6 s t slot < 16 s 1 s t low1 < 2 s 1 s t rec < 1 s t rec < resistor master
DS2890 20 of 28 b) write-zero time slot 15s resistor master (od: 2s) DS2890 60s t low0 sampling window (od: 6s) regular speed overdrive speed 60 s t low0 < t slot < 120 s 1 s t rec < 6 s t low0 < t slot < 16 s 1 s t rec < v pullup v pullup min v ih min v il max 0v t slot t rec c) read-data time slot resistor master DS2890 master sampling window regular speed overdrive speed 60 s t slot < 120 s 1 s t lowr < 15 s 0 t release < 45 s 1 s t rec < t rdv = 15 s t su < 1 s 6 s t slot < 16 s 1 s t lowr < 2 s 0 t release < 4 s 1 s t rec < t rdv = 2 s t su < 1 s v pullup v pullup min v ih min v il max 0v t slot t rec t lowr t su t rdv t release *the optimal sampling point for the master is as close as possible to the end time of the t rdv period without exceeding t rdv . for the case of a read-one time slot, this maximizes the amount of time for the pull-up resistor to recover the line to a high level. for a read-zero time slot it ensures that a read will occur before the fastest 1-wire device(s) release the line (t release = 0).
DS2890 21 of 28 figure 21. potentiometer function command flow
DS2890 22 of 28 figure 22. potentiometer function command flow (continued)
DS2890 23 of 28 figure 23. rom function command flow
DS2890 24 of 28 figure 24. rom function command flow (continued)
DS2890 25 of 28 electrical characteristics absolute maximum ratings voltage on rh, rl, wiper rela tive to ground -0.5v to +11.0v voltage on other pins relative to ground -0.5v to +6.0v operating temperature -40 o c to +85 o c storage temperature -55 o c to +125 o c soldering temperature see j-std-020a specification * this is a stress rating only and f unctional operation of the device at these or any other conditions above those indicated in the operation s ections of this specification is not implied. exposure to absolute maximum rating conditions for extended periods of time may affect reliability. recommended dc operating conditions -40 c t a +85 c parameter symbol min typ max units notes 1-wire pull-up voltage v pup 2.8 6.0 v 1 2.8 6.0 v 1,2 auxiliary supply voltage v dd -0.3 0.8 v 1,3 notes: 1. voltages are referenced to ground 2. range applicable when an auxiliary v dd supply is used 3. range applicable when an auxiliary v dd supply is not used potentiometer characteristic 2.8v v pup 6.0v, -40 c t a +85 c parameter symbol min typ max units notes resistor terminal voltage -0.3 11.0 v 1 end-to-end total resistance 100 k end-to-end resistance tolerance -25 25 % 2 wiper resistance: r wiper 3 absolute linearity 0.6 lsb 4 relative linearity 0.25 lsb 5 -3 db cutoff frequency f cutoff 100 khz temperature coefficient 800 ppm/ o c
DS2890 26 of 28 notes: 1. voltage is referenced to ground. 2. valid at 25 o c only. 3. wiper resistance is a function of operating charact eristics. see section ?potentiometer wiper resistance and charge pump considerations? for r wiper characteristics. 4. absolute linearity is a measure of wiper output volta ge versus expected wiper voltage as determined by wiper position. 5. relative linearity is a measure of the output devi ation between successive potentiometer tap points. dc electrical characteristics 2.8v v pup 6.0v, -40 c t a +85 c parameter symbol min typ max units notes 1-wire input high v ih 2.2 v 1 1-wire input low v il -0.3 0.8 v 1,2 1-wire output high v oh v pup 6.0 v 1,3 1-wire output low @ 4 ma v ol 0.4 v 1 1-wire input leakage current i l 5 a 4 v dd input current, charge pump off i dd 4.0 a 5 v dd input current, charge pump on i dd 2.0 ma 6 notes: 1. voltages are referenced to ground. 2. under certain low voltage conditions v ilmax may have to be reduced to as much as 0.5v to always guarantee a presence pulse. 3. v pup is the external 1-wire pull-up voltage. 4. input load is to ground. 5. input current when an auxiliary v dd supply is used and the charge pump is turned off. 6. input current when an auxiliary v dd supply is used and the charge pump is turned on.
DS2890 27 of 28 ac electrical characterist ics - regular 1-wire speed 2.8v v pup 6.0v, -40 c t a +85 c parameter symbol min typ max units notes time slot t slot 60 120 s write 1 low time t low1 115s write 0 low time t low0 60 120 s read low time t lowr 115s read data valid t rdv 15 s 1 release time t release 01545s read data setup t su 1s2 recovery time t rec 1s reset high time t rsth 480 s 3 reset low time t rstl 480 s 4 presence detect high t pdh 15 60 s presence detect low t pdl 60 240 s notes: 1. the optimal sampling point for the master is as close as possible to the end time of the 15 s t rdv period without exceeding t rdv . for the case of a read-one time slot, this maximizes the amount of time for the pull-up resistor to recover the line to a high level. for a read-zero time slot it ensures that a read will occur before the fastest 1-wire device(s) release the line (t release = 0). 2. read data setup time refers to the time the host must pull the 1-wire bus low to read a bit. data is guaranteed to be valid within 1 s of this falling edge. 3. an additional reset or communication sequence cannot begin until the reset high time (t rsth ) has expired. 4. the reset low time (t rstl ) should be restricted to a maximum of 960 s, to allow interrupt signaling, otherwise, it could mask or conceal interrupt pulses. ac electrical characteristics - overdrive 1-wire speed 2.8v v pup 6.0v, -40 c t a +85 c parameter symbol min typ max units notes time slot t slot 616s write 1 low time t low1 12s write 0 low time t low0 616s read low time t lowr 12s read data valid t rdv 2s1 release time t release 01.54 s read data setup t su 1s4
DS2890 28 of 28 ac electrical characteristics - overdrive 1-wire speed 2.8v v pup 6.0v, -40 c t a +85 c parameter symbol min typ max units notes recovery time t rec 1s reset high time t rsth 48 s reset low time t rstl 48 80 s presence detect high t pdh 26s presence detect low t pdl 824s notes: 1. the optimal sampling point for the master is as close as possible to the end time of the 2 s t rdv period without exceeding t rdv . for the case of a read-one time slot, this maximizes the amount of time for the pull-up resistor to recover the line to a high level. for a read-zero time slot it ensures that a read will occur before the fastest 1-wire device(s) release the line (t release = 0). 2. read data setup time refers to the time the host must pull the 1-wire bus low to read a bit. data is guaranteed to be valid within 1 s of this falling edge. 3. an additional reset or communication sequence cannot begin until the reset high time (t rsth ) has expired. 4. the reset low time (t rstl ) should be restricted to a maximum of 960 s, to allow interrupt signaling, otherwise, it could mask or conceal interrupt pulses. capacitance ta = 25 c parameter symbol min typ max units notes 1-wire pin 800 pf 1 v dd pin 10 pf resistor terminals 10 pf note: 1. capacitance on the 1-wire pin could be 800 pf when power is first applied. if a 5 k is used to pull up the 1-wire line to v pup , the capacitance will not affect communications after a 5 s charge time.

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